Circuit layout and yield

The relation between circuit layout and yield is studied. A well-known yield formula is extended to a more general yield formula, in which not necessarily every defect is fatal. A defect sensitivity function is discussed. The function contains, in principle, all information about a chip layout necessary to calculate the yield. The relation between this sensitivity function and the yield formula is explained. If the defect size distribution is known the defect sensitivity function can be used to compute an optimal shrinking factor. An example, in which several defect size distributions are used, shows that these computations are highly sensitive for the form of the defect size distribution.>