SRAM Interleaving Distance Selection With a Soft Error Failure Model

The significance of multiple cell upsets (MCUs) is revealed by sharing the soft-error test results in three major technologies, 90 nm, 65 nm, and 45 nm. The effectiveness of single-bit error correction (SEC) codes can be maximized in mitigating MCU errors when used together with the interleaving structure in memory designs. The model proposed in this paper provides failure probability to probabilistically demonstrate the benefits of various interleaving scheme selections for the memories with SEC. Grouped events such as MCU are taken into account in the proposed model by using the compound Poisson process. As a result of the proposed model, designers can perform predictive analysis of their design choices of interleaving schemes. The model successfully showed the difference in failure probability for different choices of interleaving schemes. The model behaved as the upper bound for failure probability when compared to the neutron test data with the 45-nm static-random-access memory (SRAM) design.