A 0.787 pJ/bit, 25 Mbps True Random Number Generator Based on Analog Chaotic Tent Map

This brief presents a novel lightweight and energy-efficient true random number generator (TRNG). In contrast to traditional discrete chaos-based TRNGs, the proposed design employs a source follower in a three-transistor (3T) tent map circuit to minimize the undesirable interference between different chaos stages and eliminate the need for a precise synchronization clock. A ring topology of four such cells is used to broaden the bifurcation parameter range for sustainable chaotic behavior under noise, which enables the TRNG to achieve a high output rate, while consuming a low power consumption with a very high reliability. The proposed TRNG design is fabricated using a standard 65nm CMOS process. The core of the fabricated chip occupies only 160μm. The measurement results demonstrate that the proposed TRNG consumes merely 19.68μW at a throughput of 25Mbps or equivalently an energy efficiency of 0.787pJ/bit. Furthermore, the random bit sequence generated by the TRNG successfully passes both NIST SP 800-22 and SP800-90B randomness tests without any post-processing.