FPGA Implementation of Adaptive Digital Predistorter With Fast Convergence Rate and Low Complexity for Multi-Channel Transmitters

This paper reports an adaptive digital predistorter (DPD) with fast convergence rate and low complexity for multi-channel transmitters, which is fully implemented in a field programmable gate array. The design methodology and practical implementation issues are discussed, with concerns about the impact caused by carrier power shutdown and transmission power control. The proposed DPD is composed of multiple adaptive lookup table (LUT) units of uniform structures, allowing configurability for desired memory depth. A simplified multiplier-free normalized least mean square algorithm for fast adapting the LUT is introduced. The proposed DPD is also experimentally exploited to linearize a Doherty amplifier. The adjacent channel leakage ratio reaches -60 dB for both lower and upper bands in the test applying a long-term evolution signal. It is also demonstrated in this paper that the proposed DPD shows high robustness when a multi-channel global system for mobile communications signal with occasional carrier power shutdown is applied.