Stacking fault formation in highly doped 4H-SiC epilayers during annealing

Stacking fault formation in n+ 4H-SiC epilayers (n=9×1019 cm−3) deposited on the 4H-SiC substrates (n=5×1018 cm−3) has been observed by conventional and high-resolution transmission electron microscopy (HRTEM). Formation of faults occurred during annealing in Ar at 1150 °C for 90 min. All faults were identical double layer Shockley faults formed by the glide of partial dislocations on two neighboring basal planes. The sign of the Burgers vector for several of the partial dislocations bounding the faults at the epilayer/substrate interface has been determined by HRTEM. Approximately half the dislocations had a sign corresponding to the extra half-plane inserted into the epilayer, while the other half resulted in the removal of the same half-plane from the film. In one case, two faults bounded by opposite sign dislocations were separated by only 80 nm. This result is inconsistent with mechanical stress due to the doping difference between the epilayer and the substrate as a driving force of fault expansion.