Charge Trapping in SiOx/ZrO2 and SiOx/TiO2 Gate Dielectric Stacks

The generation of traps in SiO x /ZrO2 and SiO x /TiO2 gate dielectric stacks during gate voltage stress of metal-oxide-semiconductor capacitors is investigated. The trap generation rate and trap cross section are extracted from the analysis of the gate current increase observed during the electrical stress. These data can be explained by a model based on a two-stage degradation process, i.e., (1) H+ generation in the high-permittivity gate dielectric layer by the injected electrons and (2) transport of H+ in the high permittivity material, resulting in bond breaking and generation of ZrOH or TiOH neutral centers. The threshold electron energy for H+ generation and the activation energy for H+ transport and bond breaking are extracted from fits to the experimental results.