In this paper, we present a new and simple method to process ultrathin fully depleted SOI MOSFET's. Series resistance problems in the full-wafer thinning method are presented and compared with our locally thinned process. Device design of the method is also discussed in terms of current level. The comparison of different process architectures allows us to define the best design rules for these transistors. To validate the method, experimental characteristics of locally thinned accumulation-mode MOSFET's are presented.>
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Faynot et al. (1994) studied this question.
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