Performance Analysis of the Delay-Line Clock Regenerator

A general analysis is provided for the jitter performance of a delay clock regenerator as a function of various system parameters such as modulation format, channel filtering, signal-to-noise ratio, and line delay. The novelty with respect to previous works on the same subject is that we find an expression for the jitter variance of the regenerated clock, while other studies have dealt with an upper bound to such variance. Numerical results have been checked by computer simulations.