A new theory for trap controlled, space-charge-limited-current (SCLI) diode behavior has been derived. Standard approaches have been modified so that only the drift component of current transport is considered along with the asymmetric boundary conditions required for rectification. Simple analytical expressions for the current-voltage properties were obtained for the single-trapping level case. A straightforward, numerical integration scheme was developed for the multiple trapping level situation. Application of the results to CuxS/CdS current-voltage data provides the first SCLI explanation for rectification in these devices. Electron trapping levels at 0.60, 0.44, and 0.20 eV below the conduction band edge with respective concentrations of 3(1015), 6(1014), and 3.1(1017) cm−3 were identified. These parameters compare well to electron traps reported in the literature for CuxS/CdS and gold/CdS diodes measured by deep-level-transient spectroscopy (DLTS), admittance spectroscopy, and by SCLI analysis.
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L. D. Partain (1983) studied this question.
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