A novel method that reveals the spatial distribution of border traps in III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The increase in transconductance with frequency is explored in a very wide frequency range (1 Hz-70 GHz) and a distributed RC network is used to model the oxide and trap capacitances. An evaluation of vertical InAs nanowire MOSFETs and surface-channel InGaAs MOSFETs with Al2O3/HfO2high-κ gate dielectric shows a deep border-trap density of about 1020cm-3eV-1and a near-interfacial trap density of about 1021cm-3eV-1. The latter causes an almost steplike increase in transconductance at 1-10 GHz. This demonstrates the importance of high-frequency characterization of high-κ dielectrics in III-V MOSFETs.
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Johansson et al. (2012) studied this question.
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