A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to In0.53 Ga0.47As and InP Capacitors

By taking into account simultaneously the effects of border traps and interface states, the authors model the alternating current capacitance-voltage (C-V) behavior of high-mobility substrate metal-oxide-semiconductor (MOS) capacitors. The results are validated with the experimental In0.53Ga0.47As/ high-κ and InP/high-κ (C-V) curves. The simulated C-V and conductance-voltage (G-V) curves reproduce comprehensively the experimentally measured capacitance and conductance data as a function of bias voltage and measurement frequency, over the full bias range going from accumulation to inversion and full frequency spectra from 100 Hz to 1 MHz. The interface state densities of In0.53Ga0.47As and InP MOS devices with various high-κ dielectrics, together with the corresponding border trap density inside the high-κ oxide, were derived accordingly. The derived interface state densities are consistent to those previously obtained with other measurement methods. The border traps, distributed over the thickness of the high- κ oxide, show a large peak density above the two semiconductor conduction band minima. The total density of border traps extracted is on the order of 1019cm-3. Interface and border trap distributions for InP and In0.53Ga0.47As interfaces with high-κ oxides show remarkable similarities on an energy scale relative to the vacuum reference.