Gate-Recessed Normally OFF GaN MOSHEMT With High-Temperature Oxidation/Wet Etching Using LPCVD Si3N4as the Mask

A gate-recessed normally OFF GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si3N4passivation layer. The LPCVD Si3N4serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si3N4as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843 cm2/V · s, and low-channel resistance of 0.89 Ω · mm are achieved for a normally OFF channel with LG= 1.5 μm. For 3 μm LGD, the fabricated devices exhibit a threshold voltage (Vth) of 1.35 V, a maximum drain current of ~500 mA/mm, a high ON/OFF current ratio of ~1010, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of ~10-7mA/mm up to 10 V. A high Baliga's figure of merit of 1.26 GW/cm2is achieved in devices with 10-μm gate-drain distance.