A CMOS Process-Compatible Wet-Etching Recipe for the High-k Gate Dielectrics Pr[sub 2]O[sub 3] and Pr[sub 2−x]Ti[sub x]O[sub 3]

The fabrication of complementary metal oxide semiconductor (CMOS) structures with praseodymium oxide ( Pr 2 O 3 ) or titanium-doped praseodymium oxide ( Pr 2 − x Ti x O 3 ) ( 0 ⩽ x ⩽ 1 ) layers as integrated high- k gate dielectrics requires the development of a process-compatible etching recipe. Different wet-etching processes in acid-based chemistry were evaluated and solutions of diluted sulfuric acid were identified as suitable etchants for Pr 2 O 3 and Pr 2 − x Ti x O 3 layers on Si substrates. Metal-oxide-semiconductor stacks with poly-Si as the potential gate electrode were patterned with the help of tetramethyl ammonium hydroxide as the selective etchant attacking the poly-Si gate electrode material but not the underlying Pr-based high- k gate dielectric layers.