Theoretical modeling reveals resilient bipartite synchronization in signed Schmitt-trigger oscillator networks under delay and quantization, indicating robust timing designs for digital circuits.
Signed Schmitt–trigger relaxation oscillator (STRO) arrays are attractive timing primitives, but practical interconnects introduce finite communication delay and finite-bit quantisation (e.g. sampled comparators, time-stamped links, digital bias paths). We model signed threshold injection with heterogeneous delays and uniform quantisers, and derive a delayed, quantised signed Sakaguchi–Kuramoto phase network under weak coupling. For structurally balanced sign patterns, a gauge transformation reduces the dynamics to an unsigned delayed/quantised phase model on the absolute graph. We then provide explicit sufficient conditions that guarantee practical frequency entrainment under oscillator heterogeneity (with exact entrainment as a conditional corollary), and practical bipartite phase locking for identical nodes, with lock margins that degrade gracefully with the worst-case delay and quantiser resolution. Circuit-level ‘no-chatter’ bounds are retained via hysteresis slack, yielding a compact design recipe that couples synchronisation robustness to delay/bit-budget constraints.
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Rasappan et al. (2026) studied this question.
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