TWIN: Ternary Weight and Input Neural Network Accelerators Using an Experimentally Informed Ferroelectric Carbon Nanotube FET Compact Model

Artificial intelligence systems are increasingly embedded in daily life, but they face area and power constraints. Consequently, alternatives to binary architectures are being pursued. Ternary logic is one of those solutions that offers increased data density and enhanced computational speed. However, area overhead remains a major barrier to low‐cost, energy‐efficient ternary systems. To address these challenges, we design compact and energy‐efficient ternary logic gates based on the simulated negative differential resistance behavior of an experimentally informed ferroelectric carbon nanotube field‐effect transistor (FeCNTFET) compact model. A 10nm ferroelectric thin film on (001) was experimentally fabricated and characterized, and the extracted ferroelectric parameters were incorporated into a Landau–Khalatnikov submodel coupled to a 3nm CNTFET compact model calibrated against previously reported experimental CNTFET data. Our results indicate that by using the compact ternary FeCNTFET‐based arithmetic units, the proposed Ternary neural network (TNN) accelerators require 85% fewer unit‐sized transistors and consume 72% less power than the 8‐bit integer implementation, with accuracy reductions of 3.1% and 5.1% for MNIST and CIFAR‐10, respectively. These results indicate the potential of the proposed FeCNTFET‐based TNN accelerator for energy‐ and resource‐constrained applications.