Experimental evaluation demonstrates an on-chip subradix-2 DAC accurately tests 15-bit ADC linearity with 0.5-LSB error, indicating an area-efficient alternative for self-testing.
State-of-the-art analog-to-digital converter (ADC) built-in self-test (BIST) methods relax the test stimulus linearity but require a constant voltage shift during testing. A low-cost on-chip BIST solution with a modified R2R digital-to-analog converter (DAC) structure is developed as a signal generator and a voltage shift generator for ADC linearity test. The proposed DAC is a subradix-2 R2R DAC with a constant voltage shift generation capability. The subradix-2 architecture avoids positive voltage gaps caused by random mismatches, which relaxes the DAC matching requirements and reduces the design area. The DAC is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm technology with a small area of 0.02 mm2. The matching of the 14-bit DAC is only at the 7-bit level. Measurement results show that it is capable of testing a 15-bit ADC accurately with 0.5 least-significant bit (LSB) estimation error.
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Chen et al. (2019) studied this question.
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