High reliability sensing circuit for deep submicron spin transfer torque magnetic random access memory

A high reliability offset‐tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT‐MTJ) memory. This circuit, using a triple‐stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bit‐line voltage to a predefined small bias voltage to avoid any read disturbance during the sensing operations. By using the STMicroelectronics CMOS 40 nm design kit and a precise STT‐MTJ compact model, Monte Carlo simulations have been carried out to evaluate its sensing performance.