Improved Phase-Locked Loop Technology under Non-Ideal Grid Conditions Including DC Offset

To address the limitations of traditional phase-locked loops (PLLs), including low accuracy, slow dynamic response, and structural complexity under non-ideal grid conditions, this paper proposes an enhanced PLL method based on a second-order generalized integrator (SOGI) and a sinusoidal amplitude integrator (SAI). A mathematical model is established in a two-phase rotating coordinate system to mitigate the effects of unbalanced three-phase voltages and DC offset introduced during sampling. The SOGI first eliminates negative-sequence fundamental voltages, and the SAI subsequently suppresses the DC offset components, ensuring accurate phase extraction from the positive-sequence fundamental voltage. Simulations and hardware experiments confirm that the proposed PLL achieves higher accuracy and a faster dynamic response compared to conventional methods.