Low-Temperature Atomic-Layer-Deposited High-κ Dielectric for p-Channel In0.7Ga0.3As/GaAs0.35Sb0.65Heterojunction Tunneling Field-Effect Transistor

The interface quality of a low temperature atomic-layer-deposited (ALD) HfO 2 /Al 2 O 3 bilayer high-κ gate dielectric on a GaAs 0.35 Sb 0.65 channel for heterojunction p-channel tunneling FETs is investigated. Lowering the ALD temperature from 250 to 110 °C results in improved capacitance–voltage characteristics and lower interface trap density in metal–oxide–semiconductor capacitor structures. Using the low-temperature ALD high-κ dielectric, a GaAs 0.35 Sb 0.65 /In 0.7 Ga 0.3 As heterojunction p-channel tunneling FET is demonstrated with an improved switching slope and higher on–off current ratio. X-ray photoelectron spectroscopy is performed to investigate the effect of the deposition temperature on the chemical composition of the high-κ/GaAs 0.35 Sb 0.65 interface.