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A 256-stage programmable analog-binary correlator fabricated in a combined CMOS buried n-channel CCD technology is reported. The correlator features three-level reference weighting at each stage (+1, -1, 0), low code dependent bias, automatic CCD input bias adjustment, high-speed clock drivers, and low power dissipation. Correlation performance is presented at sampling frequencies from 10 kHz to 25 MHz.
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Tower et al. (1982) studied this question.
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