Memory macrocell techniques for 1‐V battery‐operated ASICs

Low‐power ASICs with a single Ni‐Cd battery cell are necessary to implement small, lightweight.and economical portable equipment. This paper describes SRAM and mask‐ROM macrocell techniques for 1‐V battery‐operated ASICs. Synchronous specification combined with pipeline technique is employed to enhance the performance of maximum operating frequency. Six‐transistor CMOS SRAM cells are realized by using high threshold‐voltage (VTH) MOSFETs to reduce the power dissipation due to the subthreshold leakage current. Peripheral circuitry is designed with multi‐threshold‐voltage CMOS (MTCMOS) technology, which is implemented by using high‐ and low‐VTHMOSFETs. A test chip including several memory macrocells is fabricated with 0.5‐μm MTCMOS technology, and the macrocell demonstrated 30‐MHz operation at a 1‐V power supply.