Via hole technology for thin-film transistor circuits

We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.