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Experimental evaluation demonstrates higher-than-expected attenuation in a Ka-band GaN device, highlighting that transistor sizing governs step margins.
This paper presents a 3-bit distributed step attenuator for Ka-band applications in a 100 nm GaN HEMT process. Designed for a 0 to −7 dB range across 28–38 GHz, the fabricated device provides 0 to −10.9 dB with a measured insertion loss of 0.94–1.11 dB, return losses better than 10 dB, and an RMS phase error of 4.15° at 38 GHz. Every bit was realized 40 to 58 percent above its design target at both design frequencies, a deviation that simulation did not reproduce. To identify its origin, the sensitivity of the attenuation to the tuning resistor is quantified for each cell. A sweep across 5–20 Ω gives 6.5 mdB/Ω for the 1 dB cell, rising to 42.6 mdB/Ω for the 4 dB cell. In the 1 dB cell the measured step cannot be reproduced at any resistor value, which excludes resistor variation and locates the discrepancy in the switch branch. The branch on-resistance is estimated at about 81 Ω per device, placing the tuning resistors at 0.11 to 0.20 of the branch impedance. The analysis yields a design guideline: step-size margin must be secured through device sizing rather than resistor selection, with the largest margin allocated to the cells of smallest attenuation.
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Yang et al. (2026) studied this question.
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