DC Modeling and Geometry Scaling of SiC Low-Voltage MOSFETs for Integrated Circuit Design

This paper presents the SPICE model development of the static characteristics of silicon carbide (SiC) lateral n-channel and p-channel MOSFETs based on the widely used BSIM4 compact model. The methodology for length and width scaling of the MOSFETs is demonstrated. The transfer (ID-VG) and output (ID-VD) characteristics of the SiC low-voltage MOSFETs are significantly different from their Si counterparts mainly due to the presence of the interface trapped charge, and proper modifications of the dc equations are required to accurately model the characteristics. The relatively poorer quality of the oxide-semiconductor interface in a SiC MOSFET compared to Si gives rise to valid energy states inside the bandgap. The trapped charges in these interface states are responsible for mobility degradation, higher subthreshold slope (SS), soft saturation, increase in the flat band and threshold voltage, and exaggerated body effects. In this paper, the effects of the interface trapped charge on the static characteristics of the SiC MOSFETs are intensively studied and accurate compact models are developed and incorporated in the core BSIM4 dc current equations to accurately model the SiC MOSFET I-V behavior. A new parameter extraction sequence is also proposed to optimize the model and the simulated characteristics are matched with the measured characteristics of SiC MOSFET devices.