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The present work was undertaken in order to determine the effect of various thermal treatments up to 800°C and of CVD Si 3 N 4 encapsulation on the electrical characteristics of PtSi ‐ to ‐ Si contacts containing an overlay of W‐metalization. Ohmic PtSi contacts were made to four sets of p‐type Si samples doped in the 10 18 – 10 20 cm − 3 range and three sets of n‐type Si samples doped in the 10 19 – 10 20 cm − 3 range. The measured contact resistivities, p c , s , contain large spreading resistance contributions, but they establish useful upper limits to effective impedance at contact areas having dimensions of the order of 20 × 20 µ m . The measured p c , s values range from 1.1 × 10 − 6 to 7.1 × 10 − 5 ohm ‐ cm 2 for p‐type Si samples and from 9.4 × 10 − 7 to 8.4 × 10 − 6 ohm ‐ cm 2 for n‐type Si samples. No significant degradation of contacts was observed at 600° or 700°C, or upon 680°C Si 3 N 4 deposition. At 800°C (½‐hr anneal) an excessive amount of WSi 2 is formed in the contact areas. Its effects may range from no change in contact resistance to an electrical “open.” A large disagreement exists between the measured contact resistivities and those predicted by calculations based on one‐dimensional electron tunneling through a potential barrier at the metal‐semiconductor interface. A major part of the discrepancy results from extending the theory to very small (<150Aå) depletion widths for alloyed interfaces that are physically not sharp. A three‐dimensional micromodel that includes effects of nonuniform current flow and mobility differences between n‐ and p‐type Si may be more appropriate.
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A. K. Sinha (1973) studied this question.
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