A compact low-power analog front-end for DEPFET-based detector readout systems

A column-drain readout analog front end optimized for rolling-shutter DEPFET detector systems is presented. The architecture targets high-frame-rate applications demanding low-noise current signal conditioning and direct interfacing with high-speed, low-power analog-to-digital converters (ADCs). Each readout channel comprises a transimpedance preamplifier followed by a switched-capacitor fully differential amplifier, providing the signal conditioning required for differential-input ADC integration. The design employs low-power and compact circuit topologies to meet the stringent constraints of high channel density and fine pixel pitch, achieving an optimized trade-off among power consumption, noise performance, bandwidth, and silicon area. Implemented in a 65-nm CMOS process, the front end supports an input current range of 2–10 μ A and occupies a channel area of 50 × 50 μ m 2 . The fully differential output architecture enables seamless integration with high-speed ADCs capable of sampling the detector signal within ns range acquisition window. Post-layout simulations, including extended temperature corners validate the design robustness. The finalized front end achieves approximately 1 0 5 × amplification of the input current pulse, a signal bandwidth of 26 MHz per channel, a power dissipation of 1.5 mW, and an input-referred current noise of 56 nA demonstrating its suitability for next-generation DEPFET-based detector readout systems.