1 MB 8 Bit Heterogeneous SoC with DMA and Dynamic Frequency Scaling for Low-Power IoT

The growing use of battery-operated IoT edge nodes demands compact processors with efficient data movement and runtime power management. This paper presents a custom 8-bit heterogeneous SoC combining an 8-bit datapath, 20-bit physical address path, lightweight DMA, fixed-priority bus arbitration, software-defined dynamic frequency scaling (DFS), and memory mapped peripherals. It provides a flat 1-MB physical address space while retaining an 8-bit datapath. The DMA supports 20-bit source/destination addresses and up to 16-bit transfer lengths for autonomous memory-to-memory and peripheral-to-memory transfers. A programmable clock-management unit enables firmware-controlled frequency reduction through a memory- mapped divider. Implemented in modular synthesizable Verilog RTL, the SoC integrates UART, SPI, timer/PWM, GPIO, and interrupt control. Theoretical analysis shows reduced processor transfer overhead for a representative 1-KB DMA transfer, while an eightfold frequency reduction theoretically lowers frequency proportional dynamic power by 87.5% under constant supply voltage and switched capacitance. The architecture offers a compact alternative between conventional 8-bit MCUs and 32- bit embedded processors for resource-constrained IoT edge applications.