Multi‐bit storage in reset process of Phase Change Access Memory (PRAM)

A Phase Change Access Memory (PRAM) cell with stacked phase‐change layers and heater layers is prepared. Multi‐bit storage in the reset process of the PRAM is realized by this stacked structure including phase‐change layers with uniform thickness and heater layers with different thickness. The thermal simulation results show three phase‐change layers in three temperature zones, and they will transform from polycrystalline to amorphous state layer by layer. There are four levels of resistance appearing in theR–Vcharacteristics, and 2‐bit storage is realized. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)