A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET

Using two-dimensional device simulations, the electrical parameters of gated tunnel field-effect transistor (FET) are optimized with a SiGe delta doped layer in the source region. In order to prove the validity of the simulation models we compare simulation results with the experimentally realized tunnel FET on silicon and show that it gives a good match. It is shown that the incorporation of pseudomorphic strained-Si/sub 1-x/Ge/sub x/ layers leads to a significant performance increase. Furthermore, it becomes evident that the improvements are not a direct consequence of bandgap lowering but rather an indirect consequence of tunnel barrier width lowering. This leads to an asymmetry in the n- and the p-channel performance.