Interface-engineered heat dissipation in 2D PdPS transistors

High-performance two-dimensional (2D) semiconductors are promising candidates for next-generation electronics, yet the severe self-heating limits their reliable operation under high-power conditions. Herein, we demonstrate that the h- BN encapsulation provides an efficient route for the electrothermal optimization of PdPS field-effect transistors (FETs). The h -BN encapsulated devices exhibit markedly enhanced heat dissipation, showing a threshold power density of 0.2 MW/cm 2 at a current density of 0.87 MA/cm 2 and an electric field of 19 MV/m, far exceeding the 0.033 MW/cm 2 limit obtained on SiO 2 substrates. Direct temperature measurements reveal that h -BN encapsulation significantly suppresses the channel heating, with the operating temperature decreasing systematically as the h -BN thickness increases. We further measured the thermal boundary conductance (TBC) between the PdPS channel and different substrates, obtaining values of 25 MWm -2 K -1 for PdPS/oxide and 28 MWm -2 K -1 for PdPS/ h- BN. Moreover, our finite element simulations further demonstrate that the high in-plane thermal conductivity of h -BN enables efficient lateral heat spreading, which serves as the primary thermal contribution to the enhanced thermal robustness. These findings provide quantitative guidance for thermal management in high-power 2D electronic devices.