Simulation study demonstrates the realization of digital logic gates using junction-less tunnel field-effect transistors, highlighting pathways for energy-efficient nanoelectronics.
The demand for energy-efficient electronics has propelled the exploration of alternative transistor technologies, among which Tunnel Field-Effect Transistors (TFETs) have garnered significant interest as compared to MOSFETs, and our main focus is on getting a power-efficient device. This paper presents a comprehensive study on the utilization of TFETs for logic gate implementation, emphasizing their potential to revolutionize low-power digital circuits. TFETs offer a steep Sub-threshold Swing (SS) and can operate at lower supply voltages compared to conventional MOSFETs, making them ideal candidates for power-sensitive applications. We have designed and implemented the logic gates, including OR, NAND, AND and NOR gates, using a JL-TFET device. JL-TFET is implemented for OR and NAND functions by biasing two gates separately, and using the Gate-Source (Lov) overlapping method, JL-TFET is implemented for AND and NOR functions. These implementations illustrate that the distinct properties of TFETs, including ambipolar conduction and the tunneling dependency on Gate-Source/Drain overlaps, can be effectively leveraged to achieve compact logic functions.
No takes yet. Share an insight, caveat, or question.
Shah et al. (2024) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: