Answers are grounded in this paper and cite their sources.
An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate a 12-b algorithmic analog-to-digital converter in the background. At a sampling rate of 125 ksample/s and with monolithic background calibration, the peak signal-to-(noise+distortion) ratio is 71 dB, and the spurious-free dynamic range is 95 dB. The total power dissipation is 16 mW from 5 V. The active area is 5.9 mm/sup 2/ in 1.5-/spl mu/m CMOS.
No takes yet. Share an insight, caveat, or question.
Erdogan et al. (1999) studied this question.
Synapse has enriched 10 related papers. Consider them for comparative context: