Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point

This paper introduces a transregional energy model to estimate the energy consumption of digital designs for voltages widely ranging from nominal down to deep sub-threshold. The model also predicts the optimal voltage at which the minimum energy point (MEP) occurs, and the resulting minimum energy achievable under aggressive voltage scaling. The model provides the energy profile versus voltage based on a few technology-dependent parameters that are extracted through simple circuit simulations, and other few design-dependent parameters extracted from synthesis or Place&Route reports at nominal voltage only. The model captures the effect of input-dependent (e.g., switching activity), technology-dependent (e.g., corner, transistor flavor), and micro-architectural parameters (e.g., logic depth). The model exhibits a typical error below 10%, and is well suited for design exploration under wide voltage scaling, as it avoids detailed and time-consuming multi-corner and multi-voltage iterations. Also, the model provides a quick estimate of the achievable MEP for a given design. Accordingly, the proposed model is a useful tool that supports early selection of the most energy-efficient design options to meet a targeted energy profile at low voltages.