Transmitter Linearization Adaptable to Power-Varying Operation

This paper presents the design of a power-scalable digital predistorter (DPD) for transmitter architectures. The target is to accomplish the joint compensation of impairments due to the I/Q modulator and nonlinearities associated with the power amplifier, and procure a maintained linearization performance in a range of average working operation levels. The identification method for the linearizer parameters enriches the standard least-squares procedure with a synergistic integration with sparsity-based model pruning strategies. The method has been tested with a general complex-valued Volterra model applied to the linearization of two communications transmitters operating at 3.6 GHz. The linearizers designed for the two transmitters effectively provide the joint compensation of the nonlinear behavior. In addition to their good performance in terms of adjacent channel power ratio, the DPDs exhibit a wide range of power-varying adaptation.