Modeling and Analysis of Drift-Cancellation Techniques for Time-Based Integrated Resistive Sensor Interfaces

This paper presents the drift error analysis of the integrated resistive sensor interfaces and its improvement using the drift-cancellation techniques. This paper focuses on the highly digital time-domain bang-bang phase-locked loop-based architectures that-when ideal-are intrinsically resilient to the drift generated by environmental and circuit degradation effects. Nevertheless, for applications aiming at nearly zero drift, nonideal effects resulting from mismatch and nonlinearity are still creating a residual drift error of the order of 0.5% of the full scale. The feedback mechanisms of the architecture are studied under nonideal circuit conditions using system-level analysis and simulations. The residual drift error is canceled using the system-level time-based compatible techniques applied in an online fashion, without external references and with low power and area overhead due to their highly digital implementation. The system-level simulation results show that the drift error due to mismatch is attenuated within ±0.05% of the full scale, corresponding to a 10× improvement with respect to the previous publications.