A retention-tunable monolithic SOT-MRAM enabled by strain and doping engineering for unified memory hierarchy

System-on-chip designs still rely on discrete embedded Flash (eFlash) and static random access memory (SRAM), penalizing area and standby power. A unified memory that simultaneously satisfies contrasting requirements of eFlash and SRAM in data retention, write speed, and endurance remains a highly challenging task. Here, we propose a unified monolithic spin-orbit torque magnetic random access memory (SOT-MRAM) that unifies these functions with a single magnetic tunnel junction (MTJ) film stack and an identical patterning process. Doping and strain engineering enable thermal stability to range from second-scale (SRAM-like) retention to over 10 years (eFlash-like) without sacrificing endurance (>10 12 cycles) or tunneling magnetoresistance ratios. A design-technology co-optimization (DTCO) simulations at the 28 nm CMOS technology node show a 2× area reduction and an order-of-magnitude lower static power consumption than that conventional SRAM and eFlash combination. These results provide a scalable route toward wafer-level, retention-tunable MRAM that collapses memory hierarchies for energy-efficient systems.