Low-frequency noise has been experimentally characterized in the disordered insulating phase of chalcogenide-based phase-change memory (PCM) devices. An analytical model of noise based on the two-level systems (TLS) theory has been developed. In this framework we suggest that the origin of the 1/fγ noise in the conductivity of amorphous chalcogenides has to be ascribed to the TLS-induced fluctuations of the mean trap energy in the material. The model allows to quantitatively account for noise magnitude dependence on both voltage and temperature in the readout region of the memory device. Besides, our equations well describe the noise behavior as a function of the drift phenomenon, coherently with existing structural relaxation theories. Measurements and model results show that the noise-to-signal ratio (N/S) in the readout region of the cell is constant with respect to bias; hence there is no particular readout voltage that minimizes N/S. Furthermore, the analysis of noise data with cell scaling confirms that noise in PCMs is mainly due to the bulk properties of the chalcogenide employed rather than to interfacial effects.
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Beneventi et al. (2009) studied this question.
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