Packaging of multigigabit IC's introduces an input series inductance due to the bondwire which has a dominant influence on the overall IC performance. This paper describes the design and implementation of a novel input compensation circuit that both reduces the effects of the series inductance and offers the possibility to use an external termination with different impedances. Furthermore, a detailed theoretical investigation into the performance of the circuit is presented. A 7.4 Gb/s D-type flip-flop and a 4.2-GHz, 35-dB gain amplifier have been realized in a commercial 1-/spl mu/m silicon bipolar IC process with an average f/sub T/ of 11 GHz, showing the good performance of the input circuit.>
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Hageraats et al. (1994) studied this question.
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