Electrical properties of lightly doped polycrystalline silicon

The electrical properties of lightly doped polycrystalline silicon as a function of temperature have been investigated. The polycrystalline silicon was deposited by low-pressure CVD and doped by phosphorus with ion implantation. The I-V characteristic was measured over the temperature range of 20–300 K. Comparison was made between experimental data and an electrical conduction model including both thermionic emission and thermionic field emission at the grain boundaries. The grain boundary potential barrier height was found to be an increasing function of temperature below 300 K. The effect of geometrical size on the sheet resistance of these polycrystalline silicon resistors was also measured and discussed.