A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA

Adding a spin-transfer-torque (STT) magnetoresistive random-access memory (MRAM) to a static random-access memory (SRAM) cell to produce an MRAM-backed SRAM cell for a nonvolatile field-programmable gate array (FPGA) is proposed. The proposed cell reduces the time to reconfigure the FPGA following a power-down and enables fast wake-ups and power gating. With the proposed restore operation, data are recalled with no error even in the presence of mismatch. Simulation results confirm that data can be stored in the proposed cell in 80 ns and restored in less than 1 ns.