A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design

This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a subthreshold/near-threshold regime. The proposed latch provides the TNU tolerance using two restorer circuits (RCs) to hold the correct state and a three-input clocked combinational majority circuit (CMC). The RC is based on pull-up and pull-down paths, controlled by different susceptible nodes, results in better radiation hardness. We validated the proposed latch in the STMicroelectronics 65-nm CMOS technology. The postlayout parasitic extracted simulations show that, by employing the proposed latch, an average improvement of ~42% in an area-energy-delay product (AEDP) is obtained over the recently reported TNU-hardened latch (TNUHL) at a supply voltage of 0.4 V. We also validated the proposed TNUHL in a 32-nm CMOS technology node using technology computer-aided-design (TCAD) mixed-mode simulations. In the 32-nm technology, our latch can provide a TNU tolerance up to a value of linear energy transfer (LET) equal to 190 Mev-cm2/mg. The HSPICE postlayout simulations and the TCAD mixed-mode simulation results clearly show that the proposed latch effectively tolerates TNU.