25-nm p-channel vertical MOSFETs with SiGeC source-drains

The scaling of vertical p-channel MOSFETs with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFETs to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved.