Mapping of CMOS FET degradation in bias space—Application to dram peripheral devices

Mapping and visualization of all degradation modes in both n- and p-channel field effect transistors, specifically devices for dynamic random access memory periphery, is performed in the (VG, VD) bias space applicable for complementary metal–oxide–semiconductor operation. This “all-in-one” approach allows for tracking and studying in parallel all degradation regimes, including bias temperature instability, hot carrier degradation, and off-state stress, as well as the transitions between them. It should prove beneficial when developing new very large-scale integrated technologies, since it allows for simultaneous comparison and checking of all degradation regimes and promptly identifying “weak spots” of each technology option. It also allows to choose the correct criteria (voltages or fields) at a later time and postprocessing the data as necessary.