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In this article, the authors present a hardware building block for probabilistic spin logic (PSL) consisting of a probabilistic bit (p-bit) made from an embedded low-barrier unstable magnetic tunnel junction (MTJ) and a capacitive voltage adder. It was demonstrated through simulation that these interconnected building blocks can be designed to solve a small instance of the NP-complete Subset Sum Problem. —An Chen, Semiconductor Research Corporation
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Hassan et al. (2019) studied this question.
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