Simulation of GeSn/Ge tunneling field-effect transistors for complementary logic applications

GeSn/Ge tunneling field-effect transistors (TFETs) with different device configurations are comprehensively investigated by numerical simulation. The lateral PIN- and PNPN-type point-tunneling and vertical line-tunneling device structures are analyzed and compared. Both n- and p-type TFETs are optimized to construct GeSn complementary logic applications. Simulation results indicate that GeSn/Ge heterochannel and heterosource structures significantly improve the device characteristics of point- and line-TFETs, respectively. Device performance and subthreshold swing can be further improved by increasing the Sn composition. GeSn/Ge heterosource line-TFETs exhibit excellent device performance and superior inverter voltage-transfer characteristic, which make them promising candidates for GeSn complementary TFET applications.