New varieties of computer architectures, capable of solving highly demanding computational problems, are enabled by the large manufacturing scale expected from self-assembling circuit fabrication (10 12 –10 19 devices). However, these fabrication processes are in their infancy and even at maturity are expected to incur heavy yield penalties compared to conventional silicon technologies. To retain the advantages of this manufacturing scale, new architectures must efficiently use large collections of very simple circuits. This paper describes two such architectures that are enabled by self-assembly and examines their performance.
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Dwyer et al. (2004) studied this question.
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