The integration of the fast and efficient silicon p-i-n photodetectors is presented. The suggested advanced p-i-n design speeds up the detectors, avoiding slow carrier diffusion: the p+anode is arranged in a thick n$low-doped intrinsic region placed inside an n+-doped region. Two p-i-n detector concepts are compared: a plain p-i-n photodiode and a structured p-i-n fingerdiode that is optimized for shorter wavelengths. Due to this setup and a thick intrinsic region, a responsivity of R=0.25 A/W (0.42 A/W) {0.27 A/W} at a wavelength of lambda=410 nm (660 nm) {850 nm} for the p-i-n fingerdiode, a bandwidth up to f3dB=3GHz and a dark current of Idark=0.36 pA at Vp-i-n=17 V for the p-i-n photodiode could be reached. As a system-on-chip (SOC), BiCMOS circuitry is combined with the integrated photodetector to an optoelectronic integrated circuit (OEIC) as shown on an exemplary application of a 6-Gb/s monolithic optical receiver. The chips are realized in a modified 0.5 mum BiCMOS process
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Nemecek et al. (2006) studied this question.
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