An Analytical Model of Gate-All-Around Heterojunction Tunneling FET

A compact analytical drain current model considering the inversion layer and source depletion is developed for the gate-all-around (GAA) heterojunction tunneling FET (H-TFET) with staggered-gap alignment. Poisson's equations are solved to obtain the continuous surface potential profile for the GAA H-TFET first, then the drain current is derived based on Kane's model by using the tangent line approximation method, and finally, the model is verified by TCAD simulation using GaAs0.5Sb0.5/In0.53Ga0.47As GAA H-TFET and published data. The impacts of bias, gate oxide dielectric constant, and interface fixed charge on the surface potential, electric field, and IDS-VGScan be well predicted by the proposed model. The super-linear onset and saturation characteristics of IDS-VDScurves are also obtained.