Key result
The proposed FPGA-based ECG heart rate monitoring system successfully processed data in 11.336 ns using a dual-counter method and threshold comparison.
A novel FPGA-based design using a dual-counter method enables high-speed, low-power heart rate monitoring from ECG signals.
May inform FPGA-based ECG device development; leaves open clinical validation and patient outcome data.
This paper proposes a new design to monitor the Heart Rate from Electrocardiogram (ECG) signal. The proposed design is based on the concept of identifying the voltage level of the R-wave complex component of the ECG signal above a threshold level. A 100 Hertz sample rate is selected to sample the complex ECG signal.A dual-counter based calculation method is used to obtain the mathematical value of Heart Rate.The proposed FPGA based ECG Heart Rate monitoring system can operate with high performance with respect to the low-power and high speed.The system is designed using Verilog hardware design language and Xilinx XC3s500E FPGA.
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N.R. Joshi (2014) studied Heart Rate Monitoring. FPGA based ECG Heart Rate monitoring system was evaluated on Hardware processing time and resource utilization. The proposed FPGA-based ECG heart rate monitoring system successfully processed data in 11.336 ns using a dual-counter method and threshold comparison.
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