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Charge trapping characteristics of the metal-insulator-silicon (MIS) capacitors with SiO 2 /HfO 2 /Al 2 O 3 stacked dielectrics are investigated for memory applications. A capacitance-voltage hysteresis memory window as large as 7.3 V is achieved for the gate voltage sweeping of ± 12 V, and a flat-band voltage shift of 1.5 V is observed in terms of programming under 5V and 1 ms. Furthermore, the time- and voltage-dependent charge trapping characteristics are also demonstrated, the former is related to charge trapping saturation and the latter is ascribed to variable tunnelling barriers for electron injecting and discharging under different voltages.
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Zhong-Wei et al. (2008) studied this question.
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